The present invention generally relates to the design of field effect transistors (FETS) using silicon-on-insulator (SOI) technology and, more particularly, to an SOI FET with a double gate structure.
A conventional silicon on insulator (SOI) wafer includes an insulating buried oxide layer sandwiched between a thin silicon device layer above the buried oxide and bulk silicon below the buried oxide. Common methods for fabricating SOI wafers include a separation by implantation of oxygen (SIMOX) process in which oxygen is implanted into a bulk wafer at the desired depth and a wafer bonding process in which two wafers are bonded together with the oxide layer sandwiched there between and one of the two wafers is then polished to the desired device layer thickness.
SOI field effect transistor (FET) structures are fabricated within the silicon device layer. More specifically, isolation trenches within the device layer are etched and filled with insulating material to form electrically isolated xe2x80x9cislandsxe2x80x9d, each of which forms a FET body. A gate stack is then formed above a central portion of the body. Thereafter, a source region of the body and a drain region of the body, on opposing sides of the central gate, are doped to the opposite conductivity of the central channel region beneath the gate in a self aligned gate/source/drain doping process. The resulting structure includes a channel of a first conductivity positioned below the gate and between the source region and the drain region of the opposite conductivity. When a charge is applied to the gate which is above a threshold voltage, the channel depletes and current flows between the drain and the source.
An advantage of such SOI structure over conventional bulk silicon structures is improved frequency response. More specifically, the SOI FET structure has a significantly lower junction capacitance due to the reduced size of the source/channel junction and the drain/channel junction, thereby improving frequency response.
Because of a general need within the industry to continually reduce the size and cost of integrated circuit components, it is desirable to reduce the size of each FET such that a greater quantity of such FETs may be fabricated on a particular size wafer.
A problem associated with reducing the size of an SOI FET structure is: 1) a reduction in the length of the channel (distance between the source region and the drain region) degrades FET performance because of a phenomenon known as the short channel effect; and 2) a reduction in the width of the channel (dimension perpendicular to the length) shrinks the cross section of a depletion region along the bottom of the gate in which carrier flow occurs. Both such problems degrade FET performance when FET size is reduced.
More specifically, the decreased channel length permits depletion regions adjacent to the source region and the drain region to extend towards the center of the channel which increases the off state current flow through the channel (current flow when the gate potential is below threshold) and the reduced channel width tends to decrease current flow when the gate potential is above threshold.
Accordingly, there is a strong need in the art for a semiconductor field effect transistor structure which can be scaled to sub-micron dimension without significant performance degradation.
A first aspect of the present invention is to provide a self aligned double gate field effect transistor (FET). The FET comprises an active region that includes a central channel region and a source region and a drain region on opposing sides of the central channel region. An upper gate is positioned above the central channel region and isolated from the central channel region by an insulating gate oxide layer. A back gate is positioned below the central channel region and isolated from the central channel region by an insulating oxide layer which may be the insulating oxide layer of a silicon on insulator wafer. An isolation trench region is positioned about the periphery of the active region and includes a conductive via for electrically coupling the upper gate to the back gate. Both the upper gate and the back gate may extend over the same portion of the isolation trench region for electrical coupling to the via.
A second aspect of the present invention is to provide a semiconductor device including a plurality of FETs formed on a semiconductor substrate. The semiconductor substrate comprises an insulating oxide layer positioned within the semiconductor substrate and separating a device layer portion of the semiconductor substrate from a bulk portion of the semiconductor substrate. An insulating trench pattern positioned within the device layer isolates each of the plurality of FETs. Each FET comprises an active region positioned within the device layer and includes a central channel region and a source region and a drain region on opposing sides of the central channel region. An upper gate is positioned above the central channel region and isolated from the central channel region by an insulating gate oxide layer and a back gate is positioned below the central channel region and within the bulk portion of the semiconductor substrate and is isolated from the central channel region by the insulating oxide layer. A conductive via within the insulating trench pattern electrically couples the upper gate to the back gate. Both the upper gate and the back gate may extend over the same portion of the insulating trench pattern for electrical coupling to the via.
A third aspect of the present invention is to provide a method of fabricating a FET on a silicon on insulator wafer. The method includes the steps of: a) forming a disposable gate on a central portion of the surface of an active region of the wafer utilizing a first masking pattern; b) applying a mask coating to the surface of the active region; c) removing the disposable gate to expose a perforation within the mask coating; d) implanting a back gate within a bulk portion of the wafer at a location corresponding to the perforation; f) removing the mask coating; and g) forming a gate on the central portion of the surface of the active region of the wafer utilizing the first masking pattern.
The method may further include implanting a source region and a drain region on opposing sides of a central channel region utilizing the disposable gate to mask the central channel region for performing the implant. An isolation trench may be formed about the periphery of the active region to isolate the FET from other structures fabricated on the silicon on insulator wafer and an electrically conductive via may be formed within the insulating trench to electrically coupled the gate to the back gate.
The step of forming the disposable gate may include growing a gate oxide layer on the surface of the silicon on insulator wafer, depositing a layer of polysilicon on top of the gate oxide layer, forming a mask over the portion of the polysilicon layer corresponding to the disposable gate utilizing a first mask pattern, and etching an unmasked portion of the polysilicon layer.
The step of applying the mask coating may comprise applying a layer of a compound including at least one of nitride or oxide over the entire surface of the wafer and polishing the layer of compound to expose the disposable gate and the step of removing the disposable gate to form a perforation within the mask coating may comprise use of a dry etch process.
The step of forming the insulating trench pattern may include etching the insulating trench pattern through the silicon device layer above the insulating oxide layer of the wafer and filling the etched regions with an insulating compound.
The step of forming the electrically conductive via may include masking the surface of the wafer to define and expose the via, etching the insulating trench and insulating oxide layer to form the via, and filling the via with polysilicon.
In one embodiment, the first masking pattern utilized for forming the disposable gate and the gate provides for both the gate and the back gate to extend over a portion of the insulating trench pattern to provide for electrical coupling between the via and each of the gate and the back gate and the method may include a step of implanting the base substrate below the insulating trench about the periphery of the active region to provide for electrical coupling between the via and the back gate.